Jason Ho

Thesis Topic: Design of Energy-Efficient Hybrid Analog/Digital Neuromorphic Architectures

Relevant Coursework: Cross-Layer ML HW/SW Codesign, Parallel Computer Architecture, Prediction Mechanisms in Computer Architecture, ML for Computer Systems, Low Power Design

Thesis: Tools for Understanding the Computational Behaviors of Biofilms

Relevant Coursework: VLSI Design, Digital Signal Processing, Operating Systems

• Researching the co-design of hybrid analog/digital neuromorphic (brain-like) computing systems that combine the efficiency of analog computing with the scalability of a digital backend
• Investigating the use of machine learning to create surrogate models of analog circuits, resulting in 3 orders of magnitude simulation speedup over SPICE with energy, latency and behavior estimation under 7%, 8%, and 2%, respectively
• Researching tradeoffs of novel devices such as RRAMs in hybrid neuromorphic architectures for spiking neural network acceleration

• Modeled bacterial biofilm coupling interactions as Kuramoto oscillators to investigate non-conventional oscillatory computing systems
• Developed super-resolution techniques for impedance tomography on a custom imaging and stimulation platform for oscillatory computing system exploration

• Upcoming

• Characterized and modeled energy efficiency of the power management IC tree in future Oryon CPUs targeted for mobile and laptop applications

• Characterized power and performance on future APU plus discrete GPU platforms focused on power allocation algorithms between the APU and GPU on GPU-bound benchmarks
• Owned and deployed an internal data analysis tool that linked Power BI and internal databases to automate multi-phasic statistical analysis of benchmark logs, providing a 100x speedup from previous methods
• Maintained, built and ran benchmarks on 8 separate systems for power and performance characterization

• Lead verification transition for the team from VMM to UVM environment while reusing as much code as possible
• Developed firmware initialization and configuration code for read channel UVM environment with functionality for large-scale read channel testbenches

• Designed and optimized RTL block to increase ECC correction throughput in the hard drive read pipeline
• Developed VMM infrastructure to verify the new RTL block robustly

• Developed parallel signal processing algorithms and state machines on Xilinx FPGAs for analysis of tagged DNA for whole genome sequencing
• Optimized FPGA design to reduce slices by 2x, while increasing throughput by 16x to process streaming of 128 nanopore sensors

• Designed Copyright infringement scripts in Python that parsed DMCA emails, searched firewall logs, and verified infringement on University firewall traffic, saving non-technical staff over 3 hours of time per case or speedup of 30x
• Queried SQL databases to aggregate Crowdstrike data with firewall permit-deny traffic on real-time dashboards to display malicious traffic by optimizing firewall parsing by 20 times using regex

• Mentor group of 6-8 first-year Electrical and Computer Engineering graduate students through the transition to UT Austin

• Mentored master's student interested in pursuing a Ph.D. in computer architecture; Now pursuing a Ph.D. at Johns Hopkins University

• Mentor for two high school students interested in research, which culminated in a literature-review-based poster session

• Ran office hours twice a week in the computing lab to help students build RISC-V processors on Altera FPGA boards
• Held conceptual hours for students and helped guide students toward designs optimized to minimize logic, or speed

• Designed a final project for students to emulate communication across a physical channel amid noise and crosstalk on the channel.
• Held conceptual hours for students to further their understanding beyond the classroom

• Lead two lab sessions a week, teaching students Arduino and breadboarding on topics such as timers, interrupts, real-time operating systems, and sensors
• Held conceptual hours once a week for any students to come to as well
• Guided and provided advice to students for their final design projects

• Advised mentees interested in concentrating in Computer Engineering, Computer Science, or related fields on classes, research, and internship opportunities

• Helped mentees devise plans on completing concentration requirements as well as providing advice on classes, research, internship opportunities, and approach to learning

• Held weekly office hours to provide conceptual understanding of digital design, computer architecture, and programming assignments
• Helped teach students in class with interactive digital design demonstrations and embedded systems coding