Jason Ho

Ph.D. Candidate in Electrical & Computer Engineering, UT Austin

jasonchekfungho@gmail.com·(+1) 401-965-7728
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Education

University of Texas at Austin

Aug 2022 – Present
Ph.D. Electrical and Computer Engineering (Computer Architecture)GPA: 3.96

Thesis Topic: Design of Energy-Efficient Hybrid Analog/Digital Neuromorphic Architectures

University of Texas at Austin

Aug 2022 – Dec 2024
M.S. Electrical and Computer Engineering (Computer Architecture)GPA: 3.96

Coursework: Cross-Layer ML HW/SW Codesign, Parallel Computer Architecture, Prediction Mechanisms in Computer Architecture, ML for Computer Systems, Low Power Design

Brown University

Sept 2018 – May 2022
Sc.B. Computer Engineering with HonorsGPA: 3.96

Thesis: Tools for Understanding the Computational Behaviors of Biofilms

Coursework: VLSI Design, Digital Signal Processing, Operating Systems

Research Experience

Graduate Researcher, SLAM Lab — UT Austin

Aug 2022 – Present

Advisor: Prof. Andreas Gerstlauer

  • Researching co-design of hybrid analog/digital neuromorphic computing systems combining analog energy efficiency with digital backend scalability.
  • Developed machine learning surrogate models for analog circuits, achieving 3 orders of magnitude simulation speedup over SPICE while keeping energy, latency, and behavior error below 7%, 8%, and 2%.
  • Investigating device-level tradeoffs (e.g. RRAMs) in hybrid neuromorphic architectures for spiking neural network acceleration.

Undergraduate Researcher, SCALE Lab — Brown University

Jan 2021 – Jun 2022

Advisors: Prof. Sherief Reda, Prof. Jacob Rosenstein

  • Modeled bacterial biofilm coupling interactions as Kuramoto oscillators to investigate non-conventional oscillatory computing systems.
  • Developed super-resolution techniques for impedance tomography on a custom imaging and stimulation platform.

Publications

  1. J. Ho, E. Atayeter, T. Blottin, I. Joe, R. Sistrunk, B. Zhang, L. Solnica-Krezel, A. Gerstlauer, J. Wallingford, R. Gray, "Cilia.io: Computer vision and machine learning reveal spatial patterns of cilia beating dynamics in the spinal cord," Cell Reports Methods, 2026. (in review)
  2. J. Boyle, J. Ho, A. Aalund, Z. Houlton, A. Iman, I. Gonzalez, K. Jha, L. Lui, P. Shroff, R. Sam, S. Cardwell, F. Chance, A. Gerstlauer, "Bridging the Gap in Neuromorphic Co-Design with the SANA-FE Co-Simulation Framework," IEEE Computer Special Issue: Convergence in Neuromorphic Systems, 2026. (in review)
  3. J. Ho, J. Boyle, L. Liu, A. Gerstlauer, "LASANA: Large-Scale Analog Surrogate Modeling for Neuromorphic Architecture Exploration," International Symposium on Machine Learning for Computer-Aided Design (MLCAD), 2025.
  4. J. Boyle, J. Ho, M. Plagge, S. Cardwell, F. Chance, A. Gerstlauer, "Exploring Dendrites in Large-Scale Neuromorphic Architectures," International Conference for Neuromorphic Systems (ICONS), 2025.
  5. K. Hu, J. Ho, J. K. Rosenstein, "Super-Resolution Electrochemical Impedance Imaging with a 512 x 256 CMOS Sensor Array," IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), 2022.

Talks & Posters

Invited Talks

  • "LASANA: Large-Scale Analog Surrogate Modeling for Neuromorphic Architecture Exploration," Qualcomm Internal Ph.D. Talk, July 2025.

Poster Presentations

  • "LASANA: Large-Scale Analog Surrogate Modeling," 6G @ UT Symposium, Austin, TX, Nov 2025.
  • "LASANA: Large-Scale Analog Surrogate Modeling," iMAGiNE Consortium Poster Session, Austin, TX, Apr 2025.
  • "LASANA: Large-Scale Analog Surrogate Modeling," AMD Poster Session, Austin, TX, Nov 2024.
  • "LASGNA: Large-Scale Analog Surrogate Modeling," MLCAD 2024, Snowbird, UT, Sept 2024.

Engineering Experience

GPU Power Architect Intern — NVIDIA

May 2026 – Sept 2026

Upcoming internship.

CPU Power Characterization & Modeling Intern — Qualcomm

Jun 2025 – Aug 2025
  • Characterized and modeled energy efficiency of PMIC trees in future Oryon CPUs for mobile and laptop targets.

Power & Performance Lead / Architect Intern — AMD

May 2023 – Aug 2023
  • Characterized power/performance on APU + discrete GPU platforms focused on dynamic power allocation algorithms.
  • Built internal analysis tool linking Power BI and databases to automate log analysis (100x speedup).

VLSI Design & Verification Intern — Seagate Technology

May 2021 – Aug 2022
  • Led verification environment transition from VMM to UVM and authored firmware initialization code.
  • Designed and optimized RTL block to increase ECC correction throughput in hard drive read pipelines.

FPGA Engineering Intern — Nabsys

Jun 2020 – Sept 2020
  • Developed parallel signal processing state machines on Xilinx FPGAs for DNA sequencing (2x slice reduction, 16x throughput).

Honors & Service

Honors & Awards

  • NSF GRFP Honorable Mention (2024, 2022)
  • Cockrell School Fellowship, UT Austin (2022 – Present)
  • Graduate Excellence Fellow, UT Austin (2022 – Present)
  • Sigma Xi & Tau Beta Pi Honor Societies (2021, 2022)
  • Best Use of Google Cloud, Hack @ Brown (2020)

Service & Mentorship

  • ABET External Advisory Board, Brown University (2025)
  • ECE Graduate Peer Mentor, UT Austin (2023 – Present)
  • ECE Representative, UT Austin GSA (2023 – 2024)
  • Head TA, Design of Computing Systems (RISC-V/FPGA)